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Frequently asked basic questions from Digital circuit in interview!!!!
1. APPLICATIONS OF FLIP FLOP
- It is a parallel data storage element.(if we have N flip flops it will store N datas).
- It is also a serial data storage element.
- Used for serial to parallel conversion
- Also for parallel to serial conversion
- Useful in counting applications (N flip flop can be used to count 2N pulses)
- It is used for frequency division (N flip flops can be used to divide the input frequency by 2N)
- It is Used for transfer of data
2. The basic difference between a shift register and counter
Shift register has no specified sequence of states except in certain very specialized applications whereas a counter has a specified sequence of states to count.
- A counter may count in upward direction or in the downward direction which is called up/down counter respectively
- Each of the counts of a counter is called as the state of a counter
- The number of states there which counter passes before returning to the starting state is called as modules of the counter
- An n-bit counter will have n-flip flops and 2n states and it divides the input frequency by 2n. Hence it is a divide by 2n counter
- A counter which goes through all possible states is called full module counter otherwise it is called variable module counter
4.LOCK OUT CONDITION
It occurs in shortened module counters, when the counter is switched on, because of noise spikes, the counter may find itself in invalid state. In subsequent clock pulses, counter may move around invalid states and thus become useless. To avoid this external logic circuitry is provided which properly resets each flip flop.
5.HOW TO DESIGN A SYNCHRONOUS COUNTER
- Determine the number of flip flops(n): where number of states N<=2n
- Draw the state diagram showing all possible states
- Determine the type of flip flop to be used and draw excitation table
- Find the equation using Karnaugh map
- Logical circuit is drawn based on the equation
- Add two 4 bit BCD code groups
- Find if the sum is greater than 1001 (9D)
- If yes, add 0110 (6D) to this sum and generate a carry to the next decimal position
- Thus the logical circuit of BCD adder consists of 24 bit parallel adders and a correction detector circuit
7.EXCESS 3 ADDER
- Add two excess 3 code groups
- If carry = 1, add 0011(3D) to the sum of those 2 code groups
- if carry = 0, subtract 0011(3D) i.e. add 1101(13D) to the sum of those 2 code groups
8.EXCESS 3 SUBTRACTOR
- Complement the subtractend (number to be subtracted)
- Add this to minuend (number from which subtractend is to be subtracted)
- If carry = 1, result is positive. Add 011(3D) and end around carry to the result
- If carry = 0, result is negative. Subtract 0011(3D) i.e. add 1101 (13D) and take 1's complement of the result
9.PARITY BIT CHECKER / GENERATOR
At the receiving end, if the word received has even number of 1's in the odd parity system or odd number of 1's in the even parity system, then error is detected. The basic principle used is the "modulo sum of even number of 1's us always zero" and "modulo sum of odd number of 1's is always 1".
To generate an even parity bit, the 4 bits are added using 3 XOR gates and the sum bit will be the parity bit.
To generate an odd parity bit, the 4 bits are added using 3 XOR gates and the sum bit is inverted.
It is of two types
a) Static Hazard - A single variable change produces a momentary output change when no output change should occur.
b) Dynamic Hazard - Occurs in multilevel circuits when output changes for 2 adjacent input combinations. While changing, the output should change only once, but it may change 3 or more times in short intervals because of differential delays in several paths.
Hazards can be eliminated by using redundant gates.
- It uses shift registers with parallel load
- Number of full adder circuit is equal to the no. of bits in the binary numbers
- It requires one clock pulse to produce the result
- Time required does not depends upon number of bits
- It is faster
- It uses combinational circuits
- It uses shift registers
- Number of full adder circuit required is 1 and a carry flip flop
- It requires N clock pulse to produce the result
- Time required for addition depends upon number of bits
- It is slower
- It uses sequential circuits
Output of first flip flop drives the clock for second flip flop
There is no connection between output of the first flip flop and the input of the second flip flop
All flip flops are not clocked simultaneously
All flip flops are clocked simultaneously
Design and implementation is simple even for more number of states
Design and implementation is a tedious and a complex process
Low speed due to propagation delay of each flip flop
high speed because total propagation delay is equal to propagation delay of one flip flop
All flip flops are toggle flip flop
Any flip flops can be used
No extra logic gates are required
Logic gates are required based on the design
Cost is less
Cost is more