# Circuit for Generation of Dead-band / Dead-time in Electronics / Electrical Engineering

Updated on February 17, 2013

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This is Stage 3 of the design for a 50 V, 10 A DC motor drive. You can follow the link(s) below to the previous article(s) that this hub builds up on. Alternatively, you can navigate to hubs for the stages ahead.

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What is the dead-band? Why do we need it? How can I introduce dead time in my PWM waves?

Why do we need to introduce a dead band (what is a dead-band eventually) in electronic circuits? Consider the H-Bridge shown in the figure from Stage 1 of this design. Consider the 'legs' of the H Bridge from source through A1 to load to ground via A2. This is our leg A and similarly we have the leg B in the figure.

Now we have discussed in the previous stages that we shall generate a single PWM and apply it (and its inverse) to gates of the switches A1, A2, B1, B2 to operate the H Bridge to deliver controlled power to our DC Motor. The figure below shows two typical PWM waveforms that can be used to achieve this purpose in an ideal scenario.

Now according to the PWM waveforms in the figure above we are applying a high voltage (assume that high means that the switches open and the current flows) to leg A of the H Bridge for about 60% of the cycle and to leg B for about the remaining 40% of the cycle. In an ideal situation this means that the leg A will allow current to flow for 60% of the time and leg B for 40% hence having a net flow of current in leg A and delivering about 20% power to the load. As soon as the high signal is removed from gates of switches of leg A, they are open circuited in zero time. At the very same instant, switches of leg B are short circuited in zero time and the current now flows in leg B. In fact this is the result of the simulation we performed in Stage 1 of the design.

However real components never switch off or on in zero time. In fact the On time and Off time of IRF9540 and IRF540N are in tens of nano seconds. If you look at the table from Stage 2 (also shown below), you will see that both these MOSFETs switch on quicker than they switch off.

This essentially means that the switch B2, in the H Bridge figure we saw at the top, will be short circuited in about 11 ns while the switch A1 will open circuit in around 70 ns. This means that the source would be directly connected to the ground via A1 and B2 for about 59 ns! This may seem a very small time but in real time implementation of electronic circuits, this can cause a very hazardous short-circuit of the voltage source!

## The Solution!

To avoid this short-circuit scenario we need to make sure that the switches of leg A are OFF well before we turn ON the switches of leg B. This means that for some time we will apply 'low' signal to gates of all the switches in the H Bridge until they are all 'OFF' and then we will turn ON switches of our desire. This time in which all switches are OFF is called the dead-band or dead-time in electronic circuits or electrical engineering. Hence here you have the definition of dead-band / dead-time.

In the figure above you can see that for about 5 μs both signals are 'low'. This is more than enough time for our PMOS and NMOS to switch OFF. Since we are only required switching frequency of at max 15 kHz, this is an acceptable dead-time for our need.

A single PWM wave with controlled duty-cycle has been generated by the microcontroller to control the switching of our H Bridge. Now we have to manipulate and process the wave to produce four PWM waves to apply to each switch. The most essential feature of this processing will be the addition of the dead-band during transition. We achieve this by a simple RC filter and logic gates. The simulated circuit in Multisim (similar simulation in LTSpice can be performed) is shown below:

In the simulation shown in the figure above, the function generator XFG1 is used to produce the PWM wave that we shall get from the microcontroller. This wave is passed through an RC filter of R1 and C. The capacitor charges through the 650Ω resistor. The NAND gate 74LS00 detects a logic 1 when voltage is above 2.6V. Since the voltage at input rises as a transient of the charging capacitor, the delay is introduced in the output. The output of this filter is then input to a 2-input NAND gate whose other input is a 5V dc voltage (a logic 1).

To control the duration of dead-time, the values of R or C in the RC filter could be varied.

The PWM wave from the microcontroller is also passed through a NOT gate and then entered through a similar filter of R2 and C2. The output of the second NAND gate is also ‘split’ into two signals, one of which is passed through a NOT gate. All the four signals are shown in the figure below.

We see that the dead-band has been introduced in each pair of signals. The signals A and B are to be applied to the NMOS switches of our H-Bridge while the signals C and D are to be applied to PMOS switches of our H-Bridge.

Each of these signals is further passed through a buffer. This is because the output current of the gates are not enough for the opto-coupler inputs to be driven safely. The buffer supplies the current for the four opto-couplers that are to be connected ahead. From the opto-coupler onwards, begins the Power Module. This is discussed in the upcoming stages.

The insertion of the dead band may be achieved through various methods including the use of d-flip flops (if possible) but this implementation is the simplest I could think of.

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You can follow the link(s) below to the previous article(s) that this hub builds up on. Alternatively, you can navigate to hubs for the stages ahead.

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If you have any queries or want help on your project / design, fire away and I shall get back to you as soon as possible with as much help as I can provide.

Your comments are most appreciated and would be an enlightening beacon for my hubs to come.

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• keshav 3 years ago

Hello, is there any way of calculating the value of capacitor and resistor for a specific dead time using this circuit?

• dnyberg 3 years ago

I do not perceive the source of the asymmetry this circuit seeks to create, as drawn. The previous poster's diode modification would create that sort of effect by changing the shape of the shark fin curve seen at the caps.

As drawn, the best theory I can come up with is this relies on the 0.8 and 2.6 volt asymmetry of ttl logic levels, plus (undocumented) hysteresis in the nand gates. Such hysteresis is, I suspect, more reliable in a simulator than in a real world gate.

Also, I notice the ttl inputs will in fact be sourcing some current to the caps... always trying to pull the caps up even though the voltage curve of the caps are inverted relative to each other. Is this taken into account? Am I missing something?

• Ryan 4 years ago

Thanks for the info, this website helped me rig up a fast deadtime circuit for testing. I constructed your "Circuit for generation of dead-time" above, but didn't seem to get the same waveforms as your simulation. I basically got two signals that would be able to be shifted in time WRT to each other, but not a controllable deadtime between them. I changed this by adding diodes parallel to R1 and R2 in order to obtain a fast set edge time on a rising edge, but not a falling edge, and vice versa. I think your circuit right now adds delay on both rising and falling edges of the incoming signal. Am I missing something?

• Author

reddview 5 years ago

pleased to be helpful :) I hope you find all the articles enlightening.

• khurram 5 years ago

excellent desciption. to the point and easy. helped a lot in my project

thanks

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