How HBM memories work
Last week some attended a conference call under NDA where AMD detailed specifications, origin, use and characteristics of the High Bandwidth Memory (HBM) that will include in its upcoming graphics cards. In fact, they are its spearhead, its main novelty and bulwark, so they wanted to focus especially on this.
AMD has explained that the GDDR5 memory, widely used in graphics cards from previous generations soon reach a point that will not be efficient and will succumb to the power of the graphics chipset. Before this, that is already inevitable, they decided to move and create a new form factor enabling fast, efficient memory... and much more. On the ever-increasing bandwidth and power demand, the GDDR5 can not be done more small and efficient, and there is something else: the space. GDDR5 memories are put around the chip, increasing the size of the essential primary interface for high-end GPU to reach the full power. With the HBM, AMD has fixed all these aspects.
Perhaps it sounds you that the main component of the HBM is something called Interposer. Basically, the Interposer is a substrate where is introduced the Fiji chip and video memories, which in this case are stacked to save space and gain power, bandwidth and reduce consumption. Joining the VRAM and GPU in the Interposer, the proximity allows greater efficiency and, above all, faster communication to adapt the device to the new needs of bandwidth and power. It is thanks to this Interposer that the HBM are possible.
The secret of the HBM, besides this Interposer shortening times of access between different VRAM chips, are those own VRAM chips which, as we have advanced, are stacked. In one of them we can find various dies of VRAM that stack above a logical die, and all them are intercommunicated vertically together thanks to some connections called TSVs (through-silicon-vias) and microbumps, both connections used to interconnect all the layers of VRAM with the Interposer and, at the same time, with the GPU.
We have already seen the benefits of the HBM and the Interposer, but how do is interpret this in numbers? GDDR5 memory bus width is 32 bits, while the HBM is 1,024-bit. The memory speed is less: 1.750 MHz (7 Gbps) to the GDDR5 and up to 500 MHz (1 Gbps) to the HBM, something that doesn't matter too much because stacking favors final speed. In addition, there is a greater bandwidth: 28 GB/s per chip in the GDDR5 and over 100 GB/s for the HBM, and a lower voltage (1, 5V went to 1, 3V).
Something that is going to be especially striking is that the HBM space save infinitely more: If 1 GB GDDR5 could occupy a surface area of 28 x 24 mm, the same amount of VRAM in HBM occupies 7 x 5 mm, which is 94% less space that can be used for more VRAM... or simply to make the smaller graphics card. I.e. to less space with performance per watt 3 times higher than the GDDR5. Developed technologies (such as defined connectors, or the own Interposer), make an interesting technology the HBM.
up to 500 MHz (1 GBps)
up to 1750 MHz (7 GBps)
>100 GB/s per stack
up to 28 GB/s per chip