Typing Tutor Using Fpga
This article will tell you about our project basics such as the things which became the background of this research, what our topic is and how it relates to the world around it, and what kind of general principles and methodology we will be using to research our topic and evaluate our hypothesis, are all aspects of what we will cover in the introduction chapter.
We chose the topic to design a Verilog code that will not only interface LCD to FPGA but also take input from the keyboard and display it on the LCD screen. This project is implemented in different types of processors but we used limited resources to implement it. We used simple counters, memory blocks to reduce the complexity of the project.
Statement of Problem
We chose to design typing tutor, as its name suggests it is something related to typing and teaching, as tutor is related to teaching. This project can be implemented using other means but the main objective of this course was to implement it on FPGA kit.
Specifications of proposed solution
To implement the assigned task we used ISE tool and MATLAB. The kit we used was SPARTAN 3E; its specifications are discussed in coming chapters.
Purpose of the project/research
The main purpose of this project to help the users in learning the typing and simplify the interfacing of the keyboard and LCD to FPGA kit. Both of the components were to be interfaced at the same time using the Verilog Program. This program helped us learn a lot of things and specifications of the kit and all its specifications.
Applications of the project/research
This project uses keyboard and LCD which are used worldwide. Where ever keyboard is used it requires a LCD to work and display on. It can be a game, a dictionary, digital book or some business work. All it needs a modification in the code
Where ever in the world a keyboard is needed to be interfaced with an LCD to do some basic operation this project can be of use there. Be it in some rendering machine, can design a game, it can be digital book , just a little adjustments in the code can make this project a lot versatile.
Our project was divided into four parts
Part I :VGA Interfacing
Part II : Keyboard interfacing
Part III : Generating codes for memory unit of FPGA
Part IV : Removing errors after assembling all the parts
This report is organized in a way to give the reader a full overview of our project starting from the background of this project and ending at the final product The project report breakdown is as under
Complex Programmable Logic device also known as CPLD is similar to FPGA.CPLD are designed using EEPROM. It has a less complex architecture so the delays are more predictable. But these are relatively cheaper than FPGA kits.
The CPLD are less complex so we can usually interface a less dimension LCD usually of 2x16.So this board is usually used for the simple projects like displaying names or a dictionary or a simple displaying a message.
A variety of FPGA based projects are now a days being implemented a few of them are listed below
- Motor-speed controller
- Circular banner display
- Traffic Light Control
- Stop watch
- Brick Games
Project Catapult is a Microsoft venture that investigates the use of field-programmable gate arrays (FPGAs) to improve performance, reduce power consumption, and provide new capabilities in the datacenter. We have designed an FPGA board that plugs into the Microsoft-designed server that was released publically as the Open CloudServer V1.
Project Catapult started as a collaboration between Microsoft Research and Bing. Project Catapult improved the operations per second of a critical component of Bing’s search engine by nearly a factor of two. Many other applications and services can be accelerated as well. The bottom line for datacenters is more throughput and lower latencies, translating to lower power and cost, higher quality results, or a combination of both.
PROJECT DESIGN AND IMPLEMENTATION
Design of the Project Hardware/ Software
Our project title is to implement a typing tutor which takes input from the keyboard and displays it on the LCD. The hardware we used is SPARTEN 3E, PS2 Keyboard and Computer monitor screen.
The software used is ModelSim and Xilinx ISE. About ModelSim Mentor Graphics was the first to combine single kernel simulator (SKS) technology with a unified debug environment for Verilog, VHDL, and SystemC. The combination of industry-leading, native SKS performance with the best integrated debug and analysis environment make ModelSim® the simulator of choice for both ASIC and FPGA designs. The best standards and platform support in the industry make it easy to adopt in the majority of process and tool flows.
- Unified mixed language simulation engine for ease of use and performance
- Native support of Verilog, SystemVerilog for design, VHDL, and SystemC for effective verification of sophisticated design environments
- Fast time-to-debug, easy to use, multi-language debug environment
- Advanced code coverage and analysis tools for fast time to coverage closure
- Interactive and Post-Sim Debug available so same debug environment used for both
- Powerful Waveform compare for easy analysis of differences and bugs
- Advanced code coverage and analysis tools for fast time to coverage closure
Before design time is spent synthesizing and fitting the design, the RTL description is simulated to assure correct functionality. Each feature of the design should be tested to ensure that unexpected bugs have not been introduced into the design. This entails testing the specific features designed into the DUT, one at a time, as they would be used in the system. Does the counter reset properly? Will it increment properly and when expected?
First of all we searched web for the VGA interfacing , the requirements for its interfacing and all the necessary details about VGA interfacing, once our VGA was interfaced the next step was to display alphabets on the screen. For which we used matlab for code generation.
Details about hardware
The Spartan-3E family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.
Details about software/ algorithms
We used MATLAB to generate each alphabet’s binary. The alphabets were written on paint file and the dimensions were 48x64. Not only we converted the alphabet shape into binary yet also we converted the addresses of 2D array to binary bits and applied cases on it. We interfaced keyboard.
After obtaining the binary bits, we created a Verilog file out of it that we called in one of our modules.
After it we managed a LIFO (Last in first out) structure. LIFO takes input of scanned code from the entered key from the keyboard, It has a display enable bit that shows when the machine is ready to display the output. This module has 5 counters 2 for horizontal and 2 for vertical and 1 for LIFO memory to increment.
Keyboard scanning code, Keyboard input code has two portion one is Make Code and the other Break Code, at the end of every make code there comes a fo that shows the code is now completed we are scanning this fo as soon as this Fo is received we tell the acceptor to stop and display the received data.
Keyboard has two wires one of clock and the other of data. Initially both the inputs are high and when we press a key first the data pin gives a low signal and after the clock starts to generate and we start picking up the data on every negedge of clock after that comes a parity bit and then stop bit. Total bits are 11, First bit is start bit then 8 bit data then parity bit and then stop bit.
Details of final working prototype
Final product is working fine the keyboard and VGA are perfectly interfaced and are multiple times checked
TOOLS AND TECHNIQUES
Hardware used with technical specifications
Keyboard Protocol is synchronous using two pins one clock pin another data pin. Data is supposed to be sampled at falling edge of clock pin. Data is sent in packet of 11 bits. First start bit “0”, next 8 bits data, next parity then ending bit “1”.
Eight data bits are distinct for each key.
When you press a key keyboard continuously send data bits corresponding to that key continuously until it is pressed then keyboard sends ending byte ‘f0’.
The Spartan-3E family of Field-Programmable Gate Arrays (FPGAs) is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The five-member family offers densities ranging from 100,000 to 1.6 million system gates.
Software(s), simulation tool(s) used
The software used is ModelSim and Xilinx ISE. About ModelSim Mentor Graphics was the first to combine single kernel simulator (SKS) technology with a unified debug environment for Verilog. The combination of industry-leading, native SKS performance with the best integrated debug and analysis environment make ModelSim® the simulator of choice for both ASIC and FPGA designs. The best standards and platform support in the industry make it easy to adopt in the majority of process and tool flows.
Presentation of the findings
The project is working fine with both of the interfaced hardware tools perfectly and program working fine.
Results are accurate both LCD monitor and Keyboard are perfectly interfaced with no errors and work properly.
Verification of design functionalities
For verification of our results we used testbench .Design functionalities are achieved as mentioned above
The signals were trimmed due to unused variables the problem we faced in the initial stages were generating the binary bits against each alphabet and number.
If someone is actually interested to learn about VGA interfacing and Keyboard interfacing this project is so far the best project it helps to learn about the clock handling and counters of the program but if one is not good at being patient and handling counters this project is difficult for them as it requires a lot of effort in many aspects.
Perfect results obtained of the implemented design, verified using test bench.Checked our alphabets and numbers for which we wrote binary.
From this project we are now able to interface LCD and keyboard with the FPGA kit. We learnt that keyboard Protocol is synchronous using two pins one clock pin another data pin. Data is supposed to be sampled at falling edge of clock pin. Eight data bits are distinct for each key.
For LCD we searched for VGA interface on internet which helped us a lot. This project also required teamwork which helped us all to learn the idea of the interfacing of different devices to the FPGA equally.