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VHDL Code Program To Implement or To Design All The Gates Through Data Flow Modelling

Updated on February 20, 2013

In this Program, we have realized all the logic gates such as AND , Or , NOT etc. These logic gates have been designed by VHDL using Program Xilinx and ModelSim as the Simulator. Some Description about the Logic gates we have designed is as follows :

AND gate : It is a Logic circuit which delivers logic '1' at its Output if there is logic '1' at all its input i.e they are all driven high.

OR gate : It is a Logic circuit which delivers logic '0' at its Output if there is logic '0' at all its input i.e they are all driven low.

NOT Gate : It is a logic gate which always give output complement to its input i.e if logic '1' is given as input , then logic '0' will appear at the output terminal.

NAND Gate : It is a Logic circuit which delivers logic '0' at its Output if there is logic '1' at all its input i.e they are all driven high.

NOR Gate : It is a Logic circuit which delivers logic '1' at its Output if there is logic '0' at all its input i.e they are all driven low.

EX-OR (Exclusive OR) : It is a Logic circuit which delivers logic '0' at its Output if its inputs are equal but if the inputs are unequal, then its output is at logic '1'.

EX-NOR (Exclusive -NOR) gate : It is a Logic circuit which delivers logic '0' at its Output if its inputs are not equal but if the inputs are equal, then its output is at logic '1'.

VHDL Source Code For Realization Of all gates :

library IEEE;		--predefined libraries and packages
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity All_gates is			--port declaration
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           anding : out  STD_LOGIC;
           oring : out  STD_LOGIC;
           xoring : out  STD_LOGIC;
      	   nota : out  STD_LOGIC;
           notb : out  STD_LOGIC;
      	   xnoring : out  STD_LOGIC;
     	   nanding : out  STD_LOGIC;
           noring : out  STD_LOGIC);
end All_gates;		--end
architecture Behavioral of All_gates is	   --architecture body
begin
anding<=a and b;
oring<=a or b;
nota<=not a;
notb<=not b;
xoring<=a xor b;
xnoring<=a xnor b;
nanding<=a nand b;
noring<=a nor b;
end Behavioral;		--end

Output Screenshot :

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